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general description the max19706 is an ultra-low-power, mixed-signal ana- log front-end (afe) designed for power-sensitive com- munication equipment. optimized for high dynamic performance at ultra-low power, the device integrates a dual, 10-bit, 22msps receive (rx) adc; dual, 10-bit, 22msps transmit (tx) dac; three fast-settling 12-bit aux- dac channels for ancillary rf front-end control; and a 10-bit, 333ksps housekeeping aux-adc. the typical operating power in tx-rx fast mode is 49.5mw at a 22mhz clock frequency. the rx adcs feature 54.6db snr and 75.6dbc sfdr at a 5.5mhz input frequency with a 22mhz clock frequen- cy. the analog i/q input amplifiers are fully differential and accept 1.024v p-p full-scale signals. typical i/q channel matching is ?.12 phase and ?.01db gain. the tx dacs feature 72.6dbc sfdr at f out = 2.2mhz and f clk = 22mhz. the analog i/q full-scale output volt- age is ?00mv differential. the tx dac common-mode dc level is programmable from 0.9v to 1.35v. the i/q channel offset is adjustable. the typical i/q channel matching is ?.02db gain and ?.1 phase. the rx adc and tx dac share a single, 10-bit parallel, high-speed digital bus allowing half-duplex operation for time-division duplex (tdd) applications. a 3-wire serial interface controls power-management modes, the aux- dac channels, and the aux-adc channels. the max19706 operates on a single +2.7v to +3.3v ana- log supply and +1.8v to +3.3v digital i/o supply. the max19706 is specified for the extended (-40? to +85?) temperature range and is available in a 48-pin, thin qfn package. the selector guide at the end of the data sheet lists other pin-compatible versions in this afe family. applications wimax (sm) and wi-bro cpes 802.11a/b/g wlan voip terminals portable communication equipment wimax is a service mark of bandwidth.com, inc. features ? dual, 10-bit, 22msps rx adc and dual, 10-bit, 22msps tx dac ? ultra-low power 49.5mw at f clk = 22mhz, fast mode 39.3mw at f clk = 22mhz, slow mode low-current standby and shutdown modes ? programmable tx dac common-mode dc level and i/q offset trim ? excellent dynamic performance snr = 54.6db at f in = 5.5mhz (rx adc) sfdr = 72.6dbc at f out = 2.2mhz (tx dac) ? three 12-bit, 1? aux-dacs ? 10-bit, 333ksps aux-adc with 4:1 input mux and data averaging mode ? excellent gain/phase match ?.12 phase, ?.01db gain (rx adc) at f in = 5.5mhz ? multiplexed parallel digital i/o ? serial-interface control ? versatile power-control circuits shutdown, standby, idle, tx/rx disable ? miniature 48-pin thin qfn package (7mm x 7mm x 0.8mm) max19706 10-bit, 22msps, ultra-low-power analog front-end ________________________________________________________________ maxim integrated products 1 19-3867; rev 0; 10/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part* pin-package pkg code MAX19706ETM 48 thin qfn-ep** t4877-4 MAX19706ETM+ 48 thin qfn-ep** t4877-4 * all devices are specified over the -40? to +85? operating range. ** ep = exposed paddle. + denotes lead-free package. d9 d8 d6 ov dd d4 d3 d2 d0 d1 ognd d5 d7 v dd idn idp gnd v dd qdn qdp refn exposed paddle (gnd) refin dac1 com dac2 37 38 39 40 41 42 43 44 45 46 47 48 1234 5 67 89 10 24 23 22 21 20 19 18 17 16 15 14 13 adc1 adc2 v dd gnd v dd cs sclk din t/r shdn dout dac3 thin qfn max19706 top view refp v dd iap ian gnd clk gnd v dd qan qap v dd gnd 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pin configuration functional diagram and selector guide appear at end of data sheet.
max19706 10-bit, 22msps, ultra-low-power analog front-end 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd, ov dd to ognd ..............................-0.3v to +3.6v gnd to ognd.......................................................-0.3v to +0.3v iap, ian, qap, qan, idp, idn, qdp, qdn, dac1, dac2, dac3 to gnd......................-0.3v to v dd adc1, adc2 to gnd .................................-0.3v to (v dd + 0.3v) refp, refn, refin, com to gnd ............-0.3v to (v dd + 0.3v) d0?9, dout, t/ r , shdn , sclk, din, cs , clk to ognd ......................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 48-pin thin qfn (derate 27.8mw/? above +70?) .....2.22w thermal resistance ja ..................................................36?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage v dd 2.7 3.0 3.3 v output supply voltage ov dd 1.8 v dd v ext1-tx, ext3-tx, and spi2-tx states; transmit dac operating mode (tx): f clk = 22mhz, f out = 2.2mhz on both channels; aux-dacs on and at midscale, aux-adc on 11.3 ext2-tx, ext4-tx, and spi4-tx states; transmit dac operating mode (tx): f clk = 22mhz, f out = 2.2mhz on both channels; aux-dacs on and at midscale, aux-adc on 16.5 20 ext1-rx, ext4-rx, and spi3-rx states; receive adc operating mode (rx): f clk = 22mhz, f in = 5.5mhz on both channels; aux-dacs on and at midscale, aux-adc on 15.6 19 v dd supply current ext2-rx, ext3-rx, and spi1-rx states; receive adc operating mode (rx): f clk = 22mhz, f in = 5.5mhz on both channels; aux-dacs on and at midscale, aux-adc on 13.1 ma
max19706 10-bit, 22msps, ultra-low-power analog front-end _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units standby mode: clk = 0 or ov dd ; aux-dacs on and at midscale, aux-adc on 35 idle mode: f clk = 22mhz; aux-dacs on and at midscale, aux-adc on 812 ma v dd supply current shutdown mode: clk = 0 or ov dd 0.8 ? ext1-rx, ext2-rx, ext3-rx, ext4-rx, spi1-rx, spi3-rx states; receive adc operating mode (rx): f clk = 22mhz, f in = 5.5mhz on both channels; aux-dacs on and at midscale, aux-adc on 4.8 ma ext1-tx, ext2-tx, ext3-tx, ext4-tx, spi2-tx, spi4-tx states; transmit dac operating mode (tx): f clk = 22mhz, f out = 2.2mhz on both channels; aux-dacs on and at midscale, aux-adc on 247 standby mode: clk = 0 or ov dd ; aux- dacs on and at midscale, aux-adc on 0.7 idle mode: f clk = 22mhz; aux-dacs on and at midscale, aux-adc on 37.8 ov dd supply current shutdown mode: clk = 0 or ov dd 0.7 ? rx adc dc accuracy resolution n 10 bits integral nonlinearity inl ?.9 lsb differential nonlinearity dnl ?.45 lsb offset error residual dc offset error -5 ? +5 %fs gain error include reference error -5 ?.85 +5 %fs dc gain matching -0.15 ?.001 +0.15 db offset matching ?.4 lsb gain temperature coefficient ?7 ppm/? offset error (v dd ?%) ? lsb power-supply rejection psrr gain error (v dd ?%) ?.06 %fs
max19706 10-bit, 22msps, ultra-low-power analog front-end 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units rx adc analog input input differential range v id differential or single-ended inputs ?.512 v input common-mode voltage range v cm v dd / 2 v r in switched capacitor load 245 k ? input impedance c in 5pf rx adc conversion rate maximum clock frequency f clk (note 2) 22 mhz channel i 5 data latency (figure 3) channel q 5.5 clock cycles rx adc dynamic characteristics (note 3) f in = 5.5mhz, f clk = 22mhz 53 54.6 signal-to-noise ratio snr f in = 13mhz, f clk = 22mhz 54.5 db f in = 5.5mhz, f clk = 22mhz 52.9 54.6 signal-to-noise and distortion sinad f in = 13mhz, f clk = 22mhz 54.4 db f in = 5.5mhz, f clk = 22mhz 64 75.6 spurious-free dynamic range sfdr f in = 13mhz, f clk = 22mhz 76.3 dbc f in = 5.5mhz, f clk = 22mhz -78.7 third-harmonic distortion hd3 f in = 13mhz, f clk = 22mhz -77.9 dbc intermodulation distortion imd f 1 = 1.8 mhz, -7dbfs; f 2 = 1.0mhz, -7dbfs -70 dbc third-order intermodulation distortion im3 f 1 = 1.8mhz, -7dbfs; f 2 = 1.0mhz, -7dbfs -76.7 dbc f in = 5.5mhz, f clk = 22mhz -72.4 -63 total harmonic distortion thd f in = 13mhz, f clk = 22mhz -73.5 dbc aperture delay 3.5 ns overdrive recovery time 1.5x full-scale input 2 ns rx adc interchannel characteristics crosstalk rejection f in x ,y = 5.5m h z at - 0.5d bfs , f in x ,y = 1m h z at - 0.5d bfs ( n ote 4) -90 db amplitude matching f in = 5.5mhz at -0.5dbfs (note 5) ?.01 db phase matching f in = 5.5mhz at -0.5dbfs (note 5) ?.12 d eg r ees
max19706 10-bit, 22msps, ultra-low-power analog front-end _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units tx dac dc accuracy resolution n 10 bits integral nonlinearity inl ?.39 lsb differential nonlinearity dnl guaranteed monotonic (note 6) -1 ?.2 +1 lsb t a > +25? -4 ? +4 residual dc offset v os t a < +25? -5 ? +5 mv t a > +25? -30 +30 full-scale gain error include reference error (peak-to-peak error) t a < +25? -40 +40 mv tx dac dynamic performance dac conversion rate f clk (note 2) 22 mhz in-band noise density n d f out = 2.2mhz, f clk = 22mhz -130.1 dbc/hz third-order intermodulation distortion im3 f 1 = 2mhz, f 2 = 2.2mhz 84 dbc glitch impulse 10 pv s spurious-free dynamic range to nyquist sfdr f clk = 22mhz, f out = 2.2mhz 61 72.6 dbc total harmonic distortion to nyquist thd f clk = 22mhz, f out = 2.2mhz -70.2 -60 db signal-to-noise ratio to nyquist snr f clk = 22mhz, f out = 2.2mhz 59.7 db tx dac interchannel characteristics i-to-q output isolation f outx,y = 2mhz, f outx,y = 2.2mhz 90 db t a > +25? -0.3 ?.02 +0.3 gain mismatch between dac outputs measured at dc t a < +25? -0.38 +0.38 db phase mismatch between dac outputs f out = 2.2mhz, f clk = 45mhz ?.1 d eg r ees differential output impedance 800 ? tx dac analog output full-scale output voltage v fs ?00 mv bits cm1 = 0, cm0 = 0 (default) 1.29 1.35 1.41 bits cm1 = 0, cm0 = 1 1.2 bits cm1 = 1, cm0 = 0 1.05 output common-mode voltage v com bits cm1 = 1, cm0 = 1 0.9 v
max19706 10-bit, 22msps, ultra-low-power analog front-end 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units rx adc?x dac interchannel characteristics receive transmit isolation rx adc f ini = f inq = 5.5mhz, tx dac f outi = f outq = 2.2mhz, f clk = 22mhz 85 db auxiliary adc (adc1, adc2) resolution n 10 bits ad1 = 0 (default) 2.048 full-scale reference v ref ad1 = 1 v dd v analog input range 0 to v ref v analog input impedance at dc 500 k ? input-leakage current measured at unselected input from 0 to v ref ?.1 a gain error ge includes reference error -5 +5 %fs zero-code error ze 2 mv differential nonlinearity dnl ?.53 lsb integral nonlinearity inl ?.45 lsb supply current 210 ? auxiliary dacs (dac1, dac2, dac3) resolution n 12 bits integral nonlinearity inl ?.25 lsb differential nonlinearity dnl guaranteed monotonic over codes 100 to 4000 (note 6) -1.0 ?.65 +1.2 lsb gain error ge r l > 200k ? ?.7 %fs zero-code error ze ?.6 %fs output-voltage low v ol r l > 200k ? 0.1 v output-voltage high v oh r l > 200k ? 2.56 v dc output impedance dc output at midscale 4 ? settling time from 1/4 fs to 3/4 fs, within 10 lsb 1 s glitch impulse from 0 to fs transition 24 nv s rx adc?x dac timing characteristics clk rise to channel-i output data valid t doi figure 3 (note 6) 4.8 6.6 8.5 ns clk fall to channel-q output data valid t doq figure 3 (note 6) 6.6 8.8 11.1 ns i-dac data to clk fall setup time t dsi figure 5 (note 6) 10 ns
max19706 10-bit, 22msps, ultra-low-power analog front-end _______________________________________________________________________________________ 7 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units q-dac data to clk rise setup time t dsq figure 5 (note 6) 10 ns clk fall to i-dac data hold time t dhi figure 5 (note 6) 0 ns clk rise to q-dac data hold time t dhq figure 5 (note 6) 0 ns clk duty cycle 50 % clk duty-cycle variation ?5 % digital output rise/fall time 20% to 80% 2.6 ns serial-interface timing characteristics (figure 6, note 6) falling edge of cs to rising edge of first sclk time t css 10 ns din to sclk setup time t ds 10 ns din to sclk hold time t dh 0ns sclk pulse-width high t ch 25 ns sclk pulse-width low t cl 25 ns sclk period t cp 50 ns sclk to cs setup time t cs 10 ns cs high pulse width t csw 80 ns cs high to dout active high t csd bit ad0 set 200 ns cs high to dout low (aux-adc conversion time) t conv bit ad0 set, no averaging (see table 14), f clk = 22mhz, clk divider = 8 (see table 15) 4.36 ? dout low to cs setup time t dcs bit ad0, ad10 set 200 ns sclk low to dout data out t cd bit ad0, ad10 set 14.5 ns cs high to dout high impedance t chz bit ad0, ad10 set 200 ns mode-recovery timing characteristics (figure 7) from shutdown to rx mode, adc settles to within 1db sinad 82.2 shutdown wake-up time t wake , sd from shutdown to tx mode, dac settles to within 10 lsb error 26.4 ? fr om i d l e to rx m od e w i th c lk p r esent d ur i ng i d l e, ad c settl es to w i thi n 1d b s in ad 9.6 idle wake-up time (with clk) t wake , st0 from idle to tx mode with clk present during idle, dac settles to 10 lsb error 6.0 ? from standby to rx mode, adc settles to within 1db sinad 17.5 standby wake-up time t wake , st1 from standby to tx mode, dac settles to 10 lsb error 22 ?
max19706 10-bit, 22msps, ultra-low-power analog front-end 8 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units enable time from tx to rx (ext2-tx to ext2-rx, ext4-tx to ext4-rx, and spi4-tx to spi3-rx states) t enable , rx adc settles to within 1db sinad 500 ns e nab l e ti m e fr om rx to tx ( e xt1- rx to e xt1- tx, e xt4- rx to e xt4- tx, and s p i3- rx to s p i4- tx s tates) t enable , tx dac settles to within 10 lsb error 500 ns enable time from tx to rx (ext1-tx to ext1-rx, ext3-tx to ext3-rx, and spi1-tx to spi2-rx states) t enable , rx adc settles to within 1db sinad 8.1 ? e nab l e ti m e fr om rx to tx ( e xt2- rx to e xt2- tx, e xt3- rx to e xt3- tx, and s p i1- rx to s p i2- tx s tates) t enable , tx dac settles to within 10 lsb error 6.0 ? internal reference (v refin = v dd ; v refp , v refn , v com levels are generated internally) positive reference v refp - v com 0.256 v negative reference v refn - v com -0.256 v common-mode output voltage v com v dd / 2 - 0.15 v dd / 2 v dd / 2 + 0.15 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma differential reference output v ref v refp - v refn +0.490 +0.512 +0.534 v differential reference temperature coefficient reftc ?2 ppm/? buffered external reference (external v refin = 1.024v applied; v refp , v refn , v com levels are generated internally) reference input voltage v refin 1.024 v differential reference output v diff v refp - v refn 0.512 v common-mode output voltage v com v dd / 2 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma refin input current -0.7 ? refin input resistance 500 k ?
spi is a trademark of motorola, inc. max19706 10-bit, 22msps, ultra-low-power analog front-end _______________________________________________________________________________________ 9 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units digital inputs (clk, sclk, din, cs , d0?9, t/ r , shdn ) input high threshold v inh 0.7 x ov dd v input low threshold v inl 0.3 x ov dd v input leakage di in d0?9, clk, sclk, din, cs , t/ r , shdn = ognd or ov dd -1 +1 ? input capacitance dc in 5pf digital outputs (d0?9, dout) output-voltage low v ol i sink = 200? 0.2 x ov dd v output-voltage high v oh i source = 200? 0.8 x ov dd v tri-state leakage current i leak -1 +1 ? tri-state output capacitance c out 5pf note 1: specifications from t a = +25? to +85? are guaranteed by production tests. specifications from t a = +25? to -40? are guaranteed by design and characterization. note 2: the minimum clock frequency (f clk ) for the max19706 is 2mhz (typ). the minimum aux-adc sample rate clock frequency (aclk) is determined by f clk and the chosen aux-adc clock-divider value. the minimum aux-adc aclk > 2mhz / 128 = 15.6khz. the aux-adc conversion time does not include the time to clock the serial data out of the spi tm . the maximum conversion time (for no averaging, navg = 1) will be t conv (max) = (12 x 1 x 128) / 2mhz = 768?. note 3: snr, sinad, sfdr, hd3, and thd are based on a differential analog input voltage of -0.5dbfs referenced to the amplitude of the digital outputs. sinad and thd are calculated using hd2 through hd6. note 4: crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. ffts are performed on each channel. the parameter is specified as the power ratio of the first and second channel fft test tone. note 5: amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. note 6: guaranteed by design and characterization. typical operating characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) 10 9 7 8 2 3 4 5 6 1 0 rx adc channel-ia fft plot max19706 toc01 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f clk = 22mhz f ia = 5.468363mhz a ia = -0.5db 8192-point data record 10 9 7 8 2 3 4 5 6 1 0 rx adc channel-qa fft plot max19706 toc02 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f clk = 22mhz f qa = 5.468363mhz a qa = -0.5db 8192-point data record rx adc channel-ia two-tone fft plot max19706 toc05 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 10 9 7 8 2 3 4 5 6 1 0 f clk = 22mhz f 1 = 1.8mhz f 2 = 2.1mhz a ia = -7dbfs per tone 8192-point data record
max19706 10-bit, 22msps, ultra-low-power analog front-end 10 ______________________________________________________________________________________ rx adc channel-qa two-tone fft plot max19706 toc04 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 10 9 7 8 2 3 4 5 6 1 0 f clk = 22mhz f 1 = 1.8mhz f 2 = 2.1mhz a qa = -7dbfs per tone 8192-point data record rx adc signal-to-noise ratio vs. analog input frequency max19706 toc05 analog input frequency (mhz) snr (db) 90 80 60 70 20 30 40 50 10 50.5 51.0 51.5 52.0 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 50.0 0 100 ia qa rx adc signal-to-noise and distortion ratio vs. analog input frequency max19706 toc06 analog input frequency (mhz) sinad (db) 90 80 60 70 20 30 40 50 10 50.5 51.0 51.5 52.0 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 50.0 0100 ia qa rx adc total harmonic distortion vs. analog input frequency max19706 toc07 analog input frequency (mhz) thd (db) 90 80 60 70 20 30 40 50 10 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -80 0100 ia qa rx adc spurious-free dynamic range vs. analog input frequency max19706 toc08 analog input frequency (mhz) sfdr (dbc) 90 80 60 70 20 30 40 50 10 62 64 66 68 70 72 74 76 78 80 82 60 0100 qa ia rx adc signal-to-noise ratio vs. analog input amplitude max19706 toc09 analog input amplitude (dbfs) snr (db) -3 -6 -12 -9 -15 -18 34 36 38 40 42 44 46 48 50 52 54 56 58 60 32 30 -21 0 f in = 5.468363mhz ia qa rx adc signal-to-noise and distortion ratio vs. analog input amplitude max19706 toc10 analog input amplitude (dbfs) sinad (db) -3 -6 -12 -9 -15 -18 34 36 38 40 42 44 46 48 50 52 54 56 58 60 32 30 -21 0 f in = 5.468363mhz ia qa rx adc total harmonic distortion vs. analog input amplitude max19706 toc11 analog input amplitude (dbfs) thd (db) -3 -6 -9 -12 -15 -18 -75 -80 -70 -65 -60 -55 -50 -85 -21 0 ia qa f in = 5.468363mhz rx adc spurious-free dynamic range vs. analog input amplitude max19706 toc12 analog input amplitude (dbfs) sfdr (dbc) -3 -6 -9 -12 -15 -18 -21 0 55 60 65 70 75 80 85 50 f in = 5.468363mhz qa ia typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 11 rx adc signal-to-noise ratio vs. sampling rate xmax19706 toc13 sampling rate (mhz) snr (db) 53.5 54.0 54.5 55.0 55.5 56.0 53.0 f in = 5.468363mhz ia qa 19.0 16.5 14.0 11.5 9.0 6.5 4.0 1.5 21.5 rx adc signal-to-noise and distortion ratio vs. sampling rate xmax19706 toc14 sampling rate (mhz) sinad (db) f in = 5.468363mhz qa ia 19.0 16.5 14.0 11.5 9.0 6.5 4.0 53.5 54.0 54.5 55.0 55.5 56.0 53.0 1.5 21.5 rx adc total harmonic distortion vs. sampling rate max19706 toc15 sampling rate (mhz) thd (db) 19.0 16.5 11.5 14.0 6.5 9.0 4.0 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 -80 1.5 21.5 ia qa f in = 5.468363mhz rx adc spurious-free dynamic range vs. sampling rate max19706 toc16 sampling rate (mhz) sfdr (dbc) 14.0 11.5 9.0 6.5 4.0 1.5 16.5 19.0 21.5 f in = 5.468363mhz qa ia 72 73 74 75 76 77 78 79 80 81 82 83 84 85 71 70 rx adc signal-to-noise ratio vs. clock duty cycle xxmax19706 toc17 clock duty cycle (%) snr (db) 60 55 50 45 40 50.5 51.0 51.5 52.0 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 50.0 35 65 f in = 5.468363mhz ia qa rx adc signal-to-noise and distortion ratio vs. clock duty cycle xxmax19706 toc18 clock duty cycle (%) sinad (db) 60 55 50 45 40 50.5 51.0 51.5 52.0 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 50.0 35 65 f in = 5.468363mhz qa ia rx adc total harmonic distortion vs. clock duty cycle max19706 toc19 clock duty cycle (%) thd (db) -83 -82 -81 -80 -79 -78 -77 -76 -75 -74 -73 -72 -71 -70 -84 -85 ia qa f in = 5.468363mhz 60 55 50 45 40 35 65 72 73 74 75 76 77 78 79 80 81 82 83 84 85 71 70 60 55 50 45 40 35 65 rx adc spurious-free dynamic range vs. clock duty cycle max19706 toc20 clock duty cycle ( % ) sfdr (dbc) f in = 5.468363mhz ia qa rx adc offset error vs. temperature max19706 toc21 temperature ( c) offset error (%fs) 80 65 35 50 -10 5 20 -25 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 -2.0 -40 qa ia typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19706 10-bit, 22msps, ultra-low-power analog front-end 12 ______________________________________________________________________________________ tx dac spurious-free dynamic range vs. output frequency max19706 toc24 output frequency (mhz) sfdr (dbc) 10 9 8 7 6 5 4 3 2 1 73 76 79 82 85 70 011 tx dac spurious-free dynamic range vs. output amplitude max19706 toc25 output amplitude (dbfs) sfdr (dbc) -5 -10 -15 -20 -25 40 50 60 70 80 90 30 -30 0 f out = 2.2mhz tx dac channel-id two-tone spectral plot max19706 toc28 frequency ( mhz ) amplitude (dbfs) -60 -70 -50 -40 -30 -20 -10 0 -80 f 1 10 9 8 7 6 5 4 3 211 f 2 f 1 = 4mhz, f 2 = 4.5mhz tx dac channel-id spectral plot max19706 toc26 frequency (mhz) amplitude (dbfs) 10 9 78 3456 2 111 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 f id = 2.2mhz tx dac channel-qd spectral plot max19706 toc27 frequency (mhz) amplitude (dbfs) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 10 9 78 3456 2 111 f qd = 2.2mhz tx dac channel-qd two-tone spectral plot max19706 toc29 frequency (mhz) amplitude (dbfs) 10 9 78 456 3 -70 -60 -50 -40 -30 -20 -10 0 -80 211 f 1 = 4mhz, f 2 = 4.5mhz f 2 f 1 supply current vs. sampling rate max19706 toc30 sampling rate (mhz) supply current (ma) i vdd ext4-tx mode 20 18 468 1214 10 16 2 4 6 8 10 12 14 16 0 222 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) rx adc gain error vs. temperature max19706 toc22 temperature ( c) gain error (%fs) 0.2 1.6 1.0 1.4 1.8 2.0 0 0.4 0.8 1.2 1.6 80 65 35 50 -10 5 20 -25 -40 ia qa tx dac spurious-free dynamic range vs. sampling rate max19706 toc23 sampling rate (mhz) sfdr (dbc) 69 73 77 81 85 65 f out = f clk / 10 20 18 14 16 6 8 10 12 4 222
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 13 tx dac differential nonlinearity max19706 toc34 digital input code dnl (lsb) 896 768 512 640 256 384 128 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 1024 reference output voltage vs. temperature max19706 toc35 temperature ( c) v refp - v refn (v) 85 60 -15 10 35 0.505 0.510 0.515 0.520 0.500 -40 v refp - v refn aux-dac output voltage vs. output source current max19706 toc36 output source current (ma) output voltage (v) 10 1 0.1 0.01 0.5 1.0 1.5 2.0 2.5 3.0 0 0.001 100 rx adc integral nonlinearity max19706 toc31 digital output code inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 rx adc differential nonlinearity max19706 toc32 digital output code dnl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 tx dac integral nonlinearity max19706 toc33 digital input code inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
aux-dac differential nonlinearity max19706 toc40 digital input code dnl (lsb) 3072 2048 1024 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -0.8 0 4096 aux-adc integral nonlinearity max19706 toc41 digital output code inl (lsb) 896 768 512 640 256 384 128 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 2.0 -2.0 0 1024 aux-adc differential nonlinearity max19706 toc42 digital output code dnl (lsb) 896 768 512 640 256 384 128 -0.4 0 0.4 0.8 -0.8 01024 max19706 10-bit, 22msps, ultra-low-power analog front-end 14 ______________________________________________________________________________________ pin name function 1 refp upper reference voltage. bypass with a 0.33? capacitor to gnd as close to refp as possible. 2, 8, 11, 31, 33, 39, 43 v dd analog supply voltage. bypass v dd to gnd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 3 iap channel-ia positive analog input. for single-ended operation, connect signal source to iap. 4 ian channel-ia negative analog input. for single-ended operation, connect ian to com. 5, 7, 12, 32, 42 gnd analog ground. connect all gnd pins to ground plane. 6 clk conversion clock input. clock signal for both receive adcs and transmit dacs. 9 qan channel-qa negative analog input. for single-ended operation, connect qan to com. pin description aux-dac output voltage vs. output sink current max19706 toc37 output sink current (ma) output voltage (v) 10 1 0.1 0.01 0.5 1.0 1.5 2.0 2.5 3.0 0 0.001 100 aux-dac settling time max19706 toc38 500ns/div 500mv/div step from 1/4fs to 3/4fs aux-dac integral nonlinearity max19706 toc39 digital input code inl (lsb) 3072 2048 1024 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 04096 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 22mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 15 pin name function 10 qap channel-qa positive analog input. for single-ended operation, connect signal source to qap. 13?8, 21?4 d0?9 digital i/o. outputs for receive adc in rx mode. inputs for transmit dac in tx mode. d9 is the most significant bit (msb) and d0 is the least significant bit (lsb). 19 ognd output-driver ground 20 ov dd output-driver power supply. supply range from +1.8v to v dd . bypass ov dd to ognd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 25 shdn active-low shutdown input. apply logic-low to place the max19706 in shutdown. 26 dout aux-adc digital output 27 t/ r transmit/receive-mode select input. t/ r logic-low input sets the device in receive mode. a logic- high input sets the device in transmit mode. if modes are set through spi commands, the t/ r input must be pulled up to ov dd or pulled down to ognd. 28 din 3-wire serial-interface data input. data is latched on the rising edge of the sclk. 29 sclk 3-wire serial-interface clock input 30 cs 3-wire serial-interface chip-select input. logic-low enables the serial interface. 34 adc2 auxiliary adc analog input 35 adc1 auxiliary adc analog input 36 dac3 auxiliary dac3 analog output 37 dac2 auxiliary dac2 analog output 38 dac1 auxiliary dac1 analog output (afc dac, v out = 1.1v during power-up) 40, 41 idn, idp dac channel-id differential voltage output 44, 45 qdn, qdp dac channel-qd differential voltage output 46 refin reference input. connect to v dd for internal reference. 47 com common-mode voltage i/o. bypass com to gnd with a 0.33? capacitor. 48 refn negative reference i/o. rx adc conversion range is ?v refp - v refn ). bypass refn to gnd with a 0.1? capacitor. ep exposed paddle. exposed paddle is internally connected to gnd. connect ep to the gnd plane. pin description (continued) microwire is a trademark of national semiconductor corp. detailed description the max19706 integrates a dual, 10-bit rx adc and a dual, 10-bit tx dac while providing ultra-low power and high dynamic performance at a 22msps conver- sion rate. the rx adc analog input amplifiers are fully differential and accept 1.024v p-p full-scale signals. the tx dac analog outputs are fully differential with ?00mv full-scale output, selectable common-mode dc level, and adjustable i/q offset trim. the max19706 integrates three 12-bit auxiliary dac (aux-dac) channels and a 10-bit, 333ksps auxiliary adc (aux-adc) with 4:1 input multiplexer. the aux-dac channels feature 1? settling time for fast automatic gain-control (agc), variable-gain amplifier (vga), and automatic frequency-control (afc) level setting. the aux-adc features data averaging to reduce processor overhead and a selectable clock-divider to program the conversion rate. the max19706 includes a 3-wire serial interface to control operating modes and power management. the serial interface is spi and microwire compatible. the max19706 serial interface selects shutdown, idle, standby, transmit (tx), and receive (rx) modes, as well as controls aux-dac and aux-adc channels. the rx adc and tx dac share a common digital i/o to reduce the digital interface to a single, 10-bit parallel multiplexed bus. the 10-bit digital bus operates on a single +1.8v to +3.3v supply.
max19706 10-bit, 22msps, ultra-low-power analog front-end 16 ______________________________________________________________________________________ figure 1. rx adc internal t/h circuits s3b s3a com s5b s5a qap qan s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a iap ian s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b max19706 dual, 10-bit rx adc the adc uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel ia and 5.5 clock cycles for channel qa. the adc full-scale analog input range is ? ref with a v dd / 2 ( 200mv) common-mode input range. v ref is the difference between v refp and v refn . see the reference configurations section for details. input track-and-hold (t/h) circuits figure 1 displays a simplified diagram of the rx adc input track-and-hold (t/h) circuitry. both adc inputs (iap, qap, ian, and qan) can be driven either differen- tially or single-ended. match the impedance of iap and ian, as well as qap and qan, and set the input signal common-mode voltage within the v dd / 2 (?00mv) rx adc range for optimum performance.
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 17 rx adc system timing requirements figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. channel i (chi) and channel q (chq) are sampled on the rising edge of the clock signal (clk) and the resulting data is multiplexed at the d0?9 outputs. chi data is updated on the rising edge and chq data is updated on the falling edge of the clk. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for chi and 5.5 clock cycles for chq. digital input/output data (d0?9) d0?9 are the rx adc digital logic outputs when the max19706 is in receive mode. this bus is shared with the tx dac digital logic inputs and operates in half- duplex mode. d0?9 are the tx dac digital logic inputs when the max19706 is in transmit mode. the logic level is set by ov dd from 1.8v to v dd . the digital output cod- ing is offset binary (table 1). keep the capacitive load on the digital outputs d0?9 as low as possible (< 15pf) to avoid large digital currents feeding back into the ana- log portion of the max19706 and degrading its dynamic performance. buffers on the digital outputs isolate the outputs from heavy capacitive loads. adding 100 ? resis- tors in series with the digital outputs close to the max19706 will help improve rx adc and tx dac per- formance. refer to the max19707evkit schematic for an example of the digital outputs driving a digital buffer through 100 ? series resistors. during shdn, idle, and stby states, d0?9 are inter- nally pulled up to prevent floating digital inputs. to ensure no current flows through d0?9 i/o, the external bus needs to be either tri-stated or pulled up to ov dd . do not pull the external bus to ground. table 1. rx adc output codes vs. input voltage differential input voltage differential input ( lsb ) offset binary (d0?9) output decimal code v ref x 512/512 511 (+full scale - 1 lsb) 11 1111 1111 1023 v ref x 511/512 510 (+full scale - 2 lsb) 11 1111 1110 1022 v ref x 1/512 +1 10 0000 0001 513 v ref x 0/512 0 (bipolar zero) 10 0000 0000 512 -v ref x 1/512 -1 01 1111 1111 511 -v ref x 511/512 -511 (-full scale +1 lsb) 00 0000 0001 1 -v ref x 512/512 -512 (-full scale) 00 0000 0000 0 figure 2. rx adc transfer function input voltage (lsb) -1 -510 -509 1024 2 x v ref 1 lsb = v ref = v refp - v refn v ref v ref v ref v ref 0+ 1 -511 +510 +512 +511 -512 +509 (com) (com) offset binary output code (lsb) 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0011 11 1111 1111 11 1111 1110 11 1111 1101 01 1111 1111 10 0000 0000 10 0000 0001
max19706 10-bit, 22msps, ultra-low-power analog front-end 18 ______________________________________________________________________________________ figure 3. rx adc system timing diagram t doq t cl t ch t clk t doi 5 clock-cycle latency (chi) 5.5 clock-cycle latency (chq) d0?9 d0q d1i d1q d2i d2q d3i d3q d4i d4q d5i d5q d6i d6q chi chq clk table 2. tx dac output voltage vs. input codes (internal reference mode v refdac = 1.024v, external reference mode v refdac = v refin ; v fs = 400 for 800mv p-p full scale) differential output voltage ( v ) offset binary (d0?9) input decimal code 11 1111 1111 1023 11 1111 1110 1022 10 0000 0001 513 10 0000 0000 512 01 1111 1111 511 00 0000 0001 1 00 0000 0000 0 v v fs refdac 1024 1023 1023 () v v fs refdac 1024 1021 1023 () v v fs refdac 1024 3 1023 () v v fs refdac 1024 1 1023 () v v fs refdac 1024 1 1023 () ? v v fs refdac 1024 1021 1023 () ? v v fs refdac 1024 1023 1023 () ? dual, 10-bit tx dac the dual, 10-bit digital-to-analog converter (tx dac) operates with clock speeds up to 22mhz. the tx dac digital inputs, d0?9, are multiplexed on a single 10-bit bus. the voltage reference determines the tx dac full- scale output voltage. see the reference configurations section for details on setting the reference voltage. the tx dac outputs at idn, idp and qdn, qdp are biased at a 0.9v to 1.35v adjustable dc common- mode bias and designed to drive a differential input stage with 70k ? input impedance. this simplifies the analog interface between rf quadrature upconverters and the max19706. many rf upconverters require a 0.9v to 1.35v common-mode bias. the tx dac dc common-mode bias eliminates discrete level-setting resistors and code-generated level shifting while pre- serving the full dynamic range of each tx dac. the tx dac differential analog outputs cannot be used in sin- gle-ended mode because of the internally generated common-mode dc level. table 2 shows the tx dac output voltage vs. input codes. table 10 shows the selection of dc common-mode levels. see figure 4 for an illustration of the tx dac analog output levels.
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 19 the tx dac also features independent dc offset cor- rection of each i/q channel. this feature is configured through the spi interface. the dc offset correction is used to optimize sideband and carrier suppression in the tx signal path (see table 9). figure 4. tx dac common-mode dc level at idn, idp or qdn, qdp differential outputs 0 tx dac i-ch tx dac q-ch full scale = 1.55v v com = 1.35v zero scale = 1.15v 0v common-mode level select cm1 = 0, cm0 = 0 v com = 1.35v v diff = 400mv example: tx rfic input requirements ?dc common-mode bias = 1.2v (min), 1.5v (max) ?baseband input = 400mv dc-coupled 90 max19706
max19706 10-bit, 22msps, ultra-low-power analog front-end 20 ______________________________________________________________________________________ figure 5. tx dac system timing diagram t dsq t dsi q: n - 2 i: n - 1 d0?9 clk id qd q: n - 1 i: n q: n i: n + 1 n - 2 n - 1 n n - 2 n - 1 n t dhq t dhi tx dac timing figure 5 shows the relationship between the clock, input data, and analog outputs. data for the i channel (id) is latched on the falling edge of the clock signal, and q- channel (qd) data is latched on the rising edge of the clock signal. both i and q outputs are simultaneously updated on the next rising edge of the clock signal. 3-wire serial interface and operation modes the 3-wire serial interface controls the max19706 oper- ation modes as well as the three 12-bit aux-dacs and the 10-bit aux-adc. upon power-up, program the max19706 to operate in the desired mode. use the 3- wire serial interface to program the device for shut- down, idle, standby, rx, tx, aux-dac controls, or aux-adc conversion. a 16-bit data register sets the mode control as shown in table 3. the 16-bit word is composed of a3?0 control bits and d11?0 data bits. data is shifted in msb first (d11) and lsb last (a0). tables 4, 5, and 6 show the max19706 operating modes and spi commands. the serial interface remains active in all modes. spi register description program the control bits, a3?0, in the register as shown in table 3 to select the operating mode. modify a3?0 bits to select from enable-16, aux-dac1, aux-dac2, aux-dac3, ioffset, qoffset, aux-adc, enable-8, and comsel modes. enable-16 is the default operat- ing mode. this mode allows for shutdown, idle, and standby states as well as switching between fast, slow, rx, and tx modes. table 4 shows the max19706 power-management modes. table 5 shows the t/ r pin- controlled external tx-rx switching modes. table 6 shows the spi-controlled tx-rx switching modes.
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 21 table 4. power-management modes address data bits t/ r a3 a2 a1 a0 e9* e3 e2 e1 e0 pin 27 mode function (power management ) description comment 1x000 x shdn shutdown rx adc = off tx dac = off aux-dac = off aux-adc = off clk = off ref = off device is in complete shutdown. overrides t/ r pin. xx001 x idle idle rx adc = off tx dac = off aux-dac = last state clk = on ref = on fast turn-on time. moderate idle power. overrides t/ r pin. 0000 (16-bit mode) or 1000 (8-bit mode) 1x010 x stby standby rx adc = off tx dac = off aux-dac = last state aux-adc = off clk = off ref = on slow turn-on time. low standby power. overrides t/ r pin. x = don? care. * bit e9 is not available in 8-bit mode. table 3. max19706 mode control d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 register name (msb) 15 14 13 12 11 10 9 8 7 6 5 4321 (lsb) enable-16 e11 = 0 reserved e10 = 0 reserved e9 e6 e5 e4 e3 e2 e1 e0 0 0 0 0 aux-dac1 1d11 1d10 1d9 1d8 1d7 1d6 1d5 1d4 1d3 1d2 1d1 1d0 0 0 0 1 aux-dac2 2d11 2d10 2d9 2d8 2d7 2d6 2d5 2d4 2d3 2d2 2d1 2d0 0 0 1 0 aux-dac3 3d11 3d10 3d9 3d8 3d7 3d6 3d5 3d4 3d3 3d2 3d1 3d0 0 0 1 1 ioffset io5 io4 io3 io2 io1 io0 0 1 0 0 qoffset qo5 qo4 qo3 qo2 qo1 qo0 0 1 0 1 comsel cm1 cm0 0 1 1 0 aux-adc ad11 = 0 reserved ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0 1 1 1 enable-8 e3 e2 e1 e0 1 0 0 0 ?= not used.
max19706 10-bit, 22msps, ultra-low-power analog front-end 22 ______________________________________________________________________________________ table 5. external tx-rx control using t/ r pin (t/ r = 0 = rx mode, t/ r = 1 = tx mode) address data bits t/ r a3 a2 a1 a0 e3 e2 e1 e0 pin 27 state function rx to tx-tx to rx switching speed description comment 0 ext1-rx rx mode: rx adc = on tx dac = on rx bus = enable moderate power: fast rx to tx when t/ r transitions 0 to 1. 0011 1 ext1-tx fast-slow tx mode: rx adc = off tx dac = on tx bus = enable low power: slow tx to rx when t/ r transitions 1 to 0. 0 ext2-rx (default) rx mode: rx adc = on tx dac = off rx bus = enable low power: slow rx to tx when t/ r transitions 0 to 1. 0100 1 ext2-tx slow-fast tx mode: rx adc = on tx dac = on tx bus = enable moderate power: fast tx to rx when t/ r transitions 1 to 0. 0 ext3-rx rx mode: rx adc = on tx dac = off rx bus = enable low power: slow rx to tx when t/ r transitions 0 to 1. 0101 1 ext3-tx slow-slow tx mode: rx adc = off tx dac = on tx bus = enable low power: slow tx to rx when t/ r transitions 1 to 0. 0 ext4-rx rx mode: rx adc = on tx dac = on rx bus = enable moderate power: fast rx to tx when t/ r transitions 0 to 1. 0000 (16-bit mode) or 1000 (8-bit mode) 0110 1 ext4-tx fast-fast tx mode: rx adc = on tx dac = on tx bus = enable moderate power: fast tx to rx when t/ r transitions 1 to 0.
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 23 in enable-16 mode, the aux-dacs have independent control bits e4, e5, and e6, and bit e9 enables the aux- adc. table 7 shows the auxiliary dac enable codes and table 8 shows the auxiliary adc enable codes. bits e11 and e10 are reserved. program bits e11 and e10 to logic-low. modes aux-dac1, aux-dac2, and aux-dac3 select the aux-dac channels named dac1, dac2, and dac3 and hold the data inputs for each dac. bits _d11?d0 are the data inputs for each aux-dac and can be programmed through spi. the max19706 also includes two 6-bit registers that can be programmed to adjust the offsets for the tx dac i and q channels independently (see table 9). use the comsel mode to select the output common-mode voltage with bits cm1 and cm0 (see table 10). use aux-adc mode to start the auxiliary adc conversion (see the 10-bit, 333ksps auxiliary adc section for details). use enable-8 mode for faster enable and switching between shutdown, idle, and standby states as well as switching between fast, slow, and rx and tx modes. table 6. tx-rx control using spi commands address data bits t/ r a3 a2 a1 a0 e3 e2 e1 e0 pin 27 mode function (tx-rx switching speed) description comments 1011 x spi1-rx slow rx mode: rx adc = on tx dac = off rx bus = enable low power: slow rx to tx through spi command. 1100 x spi2-tx slow tx mode: rx adc = off tx dac = on tx bus = enable low power: slow tx to rx through spi command. 1101 x spi3-rx fast rx mode: rx adc = on tx dac = on rx bus = enabled moderate power: fast rx to tx through spi command. 0000 (16-bit mode) or 1000 (8-bit mode) 1110 x spi4-tx fast tx mode: rx adc = on tx dac = on tx bus = enabled moderate power: fast tx to rx through spi command. table 7. aux-dac enable table (enable-16 mode) e6 e5 e4 aux-dac3 aux-dac2 aux-dac1 000ononon 0 0 1 on on off 0 1 0 on off on 0 1 1 on off off 1 0 0 off on on 1 0 1 off on off 1 1 0 off off on 1 1 1 off off off table 8. aux-adc enable table (enable-16 mode) e9 selection 0 (default) aux-adc is powered on 1 aux-adc is powered off x = don? care.
max19706 10-bit, 22msps, ultra-low-power analog front-end 24 ______________________________________________________________________________________ shutdown mode offers the most dramatic power sav- ings by shutting down all the analog sections of the max19706 and placing the rx adc digital outputs in tri-state mode. when the rx adc outputs transition from tri-state to on, the last converted word is placed on the digital outputs. the tx dac previously stored data is lost when coming out of shutdown mode. the wake-up time from shutdown mode is dominated by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 82.2s to enter rx mode and 26.4s to enter tx mode. in idle mode, the reference and clock distribution cir- cuits are powered, but all other functions are off. the rx adc outputs are forced to tri-state. the wake-up time is 9.6? to enter rx mode and 6.0? to enter tx mode. when the rx adc outputs transition from tri- state to on, the last converted word is placed on the digital outputs. in standby mode, the reference is powered, but the rest of the device functions are off. the wake-up time from standby mode is 17.5? to enter rx mode and 22? to enter tx mode. when the rx adc outputs transition from tri-state to active, the last converted word is placed on the digital outputs. fast and slow rx and tx modes in addition to the external tx-rx control, the max19706 also features slow and fast modes for switching between rx and tx operation. in fast tx mode, the rx adc core is powered on but the adc core digital out- puts are tri-stated on the d0?9 bus; likewise, in fast rx mode, the transmit dac core is powered on but the dac core digital inputs are tri-stated on the d0?9 bus. the switching time between tx to rx or rx to tx is fast because the converters are on and do not have to recover from a power-down state. in fast mode, the switching time between rx to tx and tx to rx is 0.5s. power consumption is higher in fast mode because both the tx and rx cores are always on. to prevent table 9. offset control bits for i and q channels (ioffset or qoffset mode) bits io5?o0 when in ioffset mode, bits qo5?o0 when in qoffset mode io5/qo5 io4/qo4 io3/qo3 io2/qo2 io1/qo1 io0/qo0 offset 1 lsb = (vfs p-p / 1023) 1 1 1 1 1 1 -31 lsb 1 1 1 1 1 0 -30 lsb 1 1 1 1 0 1 -29 lsb 100010-2 lsb 100001-1 lsb 1000000mv 0 0 0 0 0 0 0mv (default) 0000011 lsb 0000102 lsb 01110129 lsb 01111030 lsb 01111131 lsb note: for transmit full scale of ?00mv: 1 lsb = (800mv p-p / 1023) = 0.7820mv. table 10. common-mode select (comsel mode) cm1 cm0 tx dac output common mode (v) 0 0 1.35 (default) 0 1 1.20 1 0 1.05 1 1 0.90
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 25 bus contention in these states, the rx adc output buffers are tri-stated during tx and the tx dac input bus is tri-stated during rx. in slow mode, the rx adc core is off during tx; likewise the tx dac is turned off during rx to yield lower power consumption in these modes. for example, the power in slow tx mode is 33.9 mw. the power consumption dur- ing rx is 39.3 mw compared to 46.8 mw power consump- tion in fast mode. however, the recovery time between states is increased. the switching time in slow mode between rx to tx is 6? and tx to rx is 8.1?. external t/ r r switching control vs. serial-interface control bit e3 in the enable-16 or enable-8 register deter- mines whether the device tx-rx mode is controlled externally through the t/ r input (e3 = low) or through the spi command (e3 = high). by default, the max19706 is in the external tx-rx control mode. in the external control mode, use the t/ r input (pin 27) to switch between rx and tx modes. using the t/ r pin provides faster switch- ing between rx and tx modes. to override the external tx-rx control, program the max19706 through the serial interface. during shdn, idle, or stby modes, the t/ r input is overridden. to restore external tx-rx control, program bit e3 low and exit the shdn, idle, or stby modes through the serial interface. when using spi commands exclusively to control tx-rx states (external t/ r pin is not used), then the t/ r pin must be pulled up to ov dd or pulled down to ognd. spi timing the serial digital interface is a standard 3-wire connec- tion compatible with spi/qspi/microwire/dsp inter- faces. set cs low to enable the serial data loading at din or output at dout. following a cs high-to-low tran- sition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (sclk). after 16 bits are loaded into the serial input register, data is transferred to the latch when cs transitions high. cs must transition high for a minimum of 80ns before the next write sequence. the sclk can idle either high or low between transitions. figure 6 shows the detailed timing diagram of the 3-wire serial interface. qspi is a trademark of motorola, inc. figure 6. serial-interface timing diagram 16-bit or 8-bit write into spi (din) 16-bit or 8-bit write into spi during aux-adc conversion 10-bit read out of aux-adc (dout) with simultaneous 16-bit write into spi (din) t chz lsb bit a0 (din) bit d1 (din) lsb msb bit d10 (din) lsb a0 dout = tri-stated when aux-adc is idle dout = active when bit ad0 is set aux-adc is busy aux-adc data ready msb bit d9 (dout) lsb bit d0 (dout) lsb bit d0 (held) dout tri- stated bit ad0 cleared d10 (16-bit) d2 (8-bit) msb d11 (16-bit) d3 (8-bit) msb bit d11 (din) t dcs t conv t csd t cs t cp t css t csw t ds t ch t cl t dh t cd sclk cs din dout
max19706 10-bit, 22msps, ultra-low-power analog front-end 26 ______________________________________________________________________________________ mode-recovery timing figure 7 shows the mode-recovery timing diagram. t wake is the wakeup time when exiting shutdown, idle, or standby mode and entering rx or tx mode. t enable is the recovery time when switching between either rx or tx mode. t wake or t enable is the time for the rx adc to settle within 1db of specified sinad performance and tx dac settling to 10 lsb error. t wake and t enable times are measured after either the 16-bit serial com- mand is latched into the max19706 by a cs transition high (spi controlled) or a t/ r logic transition (external tx-rx control). in fast mode, the recovery time is 0.5? to switch between tx or rx modes. system clock input (clk) both the rx adc and tx dac share the clk input. the clk input accepts a cmos-compatible signal level set by ov dd from 1.8v to v dd . since the interstage con- version of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. any significant clock jitter limits the snr performance of the on-chip rx adc as follows: where f in represents the analog input frequency and t aj is the time of the clock jitter. clock jitter is especially critical for undersampling applications. consider the clock input as an analog input and route away from any analog input or other digital signal lines. the max19706 clock input operates with an ov dd / 2 voltage threshold and accepts a 50% ?5% duty cycle. log snr ft = ? ? ? ? ? ? 20 1 2 in aj figure 7. mode-recovery timing diagram sclk cs din d0?9 id/qd t/r rx - > tx adc digital output sinad settles within 1db dac analog output output settles to 10 lsb error 16-bit serial data input t enable , rx external t/r control t enable , tx external t/r control t wake, sd, st_ to tx mode or t enable , tx t wake, sd, st_ to rx mode or t enable , rx t/r tx - > rx
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 27 12-bit auxiliary control dacs the max19706 includes three 12-bit aux-dacs (dac1, dac2, dac3) with 1? settling time for controlling vga, agc, and afc functions. the aux-dac output range is 0.1v to 2.56v. during power-up, the vga and agc out- puts (dac2 and dac3) are at zero. the afc dac (dac1) is at 1.1v during power-up. the aux-dacs can be independently controlled through the spi bus, except during shdn mode where the aux-dacs are turned off completely and the output voltage is set to zero. in stby and idle modes, the aux-dacs maintain the last value. on wakeup from shdn, the aux-dacs resume the last values. loading on the aux-dac outputs should be carefully observed to achieve specified settling time and stabili- ty. the capacitive load must be kept to a maximum of 5pf including package and trace capacitance. the resistive load must be greater than 200k ? . if capacitive loading exceeds 5pf, then add a 10k ? resistor in series with the output. adding the series resistor helps drive larger load capacitance (< 15pf) at the expense of slower settling time. 10-bit, 333ksps auxiliary adc the max19706 integrates a 10-bit, 333ksps aux-adc with an input 4:1 multiplexer. in the aux-adc mode reg- ister, setting bit ad0 begins a conversion with the auxil- iary adc. bit ad0 automatically clears when the conversion is complete. setting or clearing ad0 during a conversion has no effect (see table 11). bit ad1 determines the internal reference of the auxiliary adc (see table 12). bits ad2 and ad3 determine the auxil- iary adc input source (see table 13). bits ad4, ad5, and ad6 select the number of averages taken when a single start-convert command is given. the conversion time increases as the number of averages increases (see table 14). the conversion clock can be divided down from the system clock by properly setting bits ad7, ad8, and ad9 (see table 15). the aux-adc out- put data can be written out of dout by setting bit ad10 high (see table 16). the aux-adc features a 4:1 input multiplexer to allow measurements on four input sources. the input sources are selected by ad3 and ad2 (see table 13). two of the multiplexer inputs (adc1 and adc2) can be con- nected to external sources such as an rf power detec- tor like the max2208 or temperature sensor like the max6613. the other two multiplexer inputs are internal connections to v dd and ov dd that monitor the power- supply voltages. the internal v dd and ov dd connec- tions are made through integrated resistor-dividers that yield v dd / 2 and ov dd / 2 measurement results. the aux-adc voltage reference can be selected between an internal 2.048v bandgap reference or v dd (see table 12). the v dd reference selection is provided to allow measurement of an external voltage source with a full-scale range extending beyond the 2.048v level. the input source voltage range cannot extend above v dd . table 11. auxiliary adc convert table 12. auxiliary adc reference table 13. auxiliary adc input source ad0 selection 0 aux-adc idle (default) 1 aux-adc start-convert ad1 selection 0 internal 2.048v reference (default) 1 internal v dd reference ad3 ad2 aux-adc input source 0 0 adc1 (default) 0 1 adc2 10 v dd / 2 11 ov dd / 2
max19706 10-bit, 22msps, ultra-low-power analog front-end 28 ______________________________________________________________________________________ the conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. the conver- sion clock is generated from the system clock input (clk). an spi-programmable divider divides the sys- tem clock by the appropriate divisor (set with bits ad7, ad8, and ad9; see table 15) and provides the conver- sion clock to the auxiliary adc. the auxiliary adc has a maximum conversion rate of 333ksps. the maximum conversion clock frequency is 4mhz (333ksps x 12 clocks). choose the proper divider value to keep the conversion clock frequency under 4mhz, based upon the system clk frequency supplied to the max19706 (see table 15). the total conversion time (t conv ) of the auxiliary adc can be calculated as t conv = (12 x n avg x n div ) / f clk ; where n avg is the number of averages (see table 14), n div is the clk divisor (see table 15), and f clk is the system clk frequency. dout is normally in a tri-state condition. upon setting the auxiliary adc start conversion bit (bit ad0), dout becomes active and goes high, indicating that the aux- adc is busy. when the conversion cycle is complete (including averaging), the data is placed into an output register and dout goes low, indicating that the output data is ready to be driven onto dout. when bit ad10 is set (ad10 = 1), the aux-adc enters a data output mode where data is available on dout upon the next asser- tion low of cs . the auxiliary adc data is shifted out of dout (msb first) with the data transitioning on the falling edge of the serial clock (sclk). dout enters a tri-state condition when cs is deasserted high. when bit ad10 is cleared (ad10 = 0), the aux-adc data is not available on dout (see table 16). din can be written independent of dout state. a 16- bit instruction at din updates the device configuration. to prevent modifying internal registers while reading data from dout, hold din at a high state. this effec- tively writes all ones into address 1111. since address 1111 does not exist, no internal registers are affected. table 14. auxiliary adc averaging table 15. auxiliary adc clock (clk) divider table 16. auxiliary adc data output mode ad10 selection 0 aux-adc data is not available on dout (default) 1 aux-adc enters data output mode where data is available on dout ad6 ad5 ad4 aux-adc averaging 0 0 0 1 conversion (no averaging) (default) 0 0 1 average of 2 conversions 0 1 0 average of 4 conversions 0 1 1 average of 8 conversions 1 0 0 average of 16 conversions 1 0 1 average of 32 conversions 1 1 x average of 32 conversions ad9 ad8 ad7 aux-adc conversion clock 0 0 0 clk divided by 1 (default) 0 0 1 clk divided by 2 0 1 0 clk divided by 4 0 1 1 clk divided by 8 1 0 0 clk divided by 16 1 0 1 clk divided by 32 1 1 0 clk divided by 64 1 1 1 clk divided by 128 x = don? care.
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 29 reference configurations the max19706 features an internal precision 1.024v bandgap reference that is stable over the entire power- supply and temperature ranges. the refin input pro- vides two modes of reference operation. the voltage at refin (v refin ) sets the reference operation mode (table 17). in internal reference mode, connect refin to v dd . v ref is an internally generated 0.512v ?%. com, refp, and refn are low-impedance outputs with v com = v dd / 2, v refp = v dd / 2 + v ref / 2, and v refn = v dd / 2 - v ref / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. in buffered external reference mode, apply 1.024v ?0% at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd / 2, v refp = v dd / 2 + v refin / 4, and v refn = v dd / 2 - v refin / 4. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. in this mode, the tx dac full-scale output is proportional to the external reference. for example, if the v refin is increased by 10% (max), the tx dac full- scale output is also increased by 10% or ?40mv. applications information using balun transformer ac-coupling an rf transformer (figure 8) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum adc performance. connecting the center tap of the transformer to com provides a v dd / 2 dc level shift to the input. a 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. in gener- al, the max19706 provides better sfdr and thd with fully differential input signals than single-ended signals, especially for high input frequencies. in differential mode, even-order harmonics are lower as both inputs (iap, ian, qap, qan) are balanced, and each of the rx adc inputs only requires half the signal swing com- pared to single-ended mode. figure 9 shows an rf transformer converting the max19706 tx dac differen- tial analog outputs to single-ended. table 17. reference modes v refin reference mode > 0.8v x v dd internal reference mode. v ref is internally generated to be 0.512v. bypass refp, refn, and com each with a 0.33? capacitor. 1.024v ?0% buffered external reference mode. an external 1.024v ?0% reference voltage is applied to refin. v ref is internally generated to be v refin / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. figure 8. balun transformer-coupled single-ended-to- differential input drive for rx adc com iap ian 25 ? 0.1 f 0.33 f 25 ? 0.1 f v in max19706 22pf 22pf qap qan 25 ? 0.1 f 0.33 f 25 ? 0.1 f v in 22pf 22pf
max19706 10-bit, 22msps, ultra-low-power analog front-end 30 ______________________________________________________________________________________ using op-amp coupling drive the max19706 rx adc with op amps when a balun transformer is not available. figures 10 and 11 show the rx adc being driven by op amps for ac-cou- pled single-ended and dc-coupled differential applica- tions. amplifiers such as the max4454 and max4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. the op-amp circuit shown in figure 11 can also be used to interface with the tx dac differential analog outputs to provide gain or buffering. the tx dac differential ana- log outputs cannot be used in single-ended mode because of the internally generated common-mode level. also, the tx dac analog outputs are designed to drive a differential input stage with input impedance 70k ? . if single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conver- sion and select an amplifier with proper input common- mode voltage range. tdd mode the max19706 is optimized to operate in tdd applica- tions. when fast mode is selected, the max19706 can switch between tx and rx modes through the t/ r pin in typically 0.5?. the rx adc and tx dac operate independently. the rx adc and tx dac digital bus are shared forming a single 10-bit parallel bus. using the 3- wire serial interface or external t/r pin, select between rx mode to enable the rx adc or tx mode to enable the tx dac. when operating in rx mode, the tx dac bus is not enabled and in tx mode the rx adc bus is tri-stated, eliminating any unwanted spurious emissions and preventing bus contention. in tdd mode, the max19706 uses 49.5mw power at f clk = 22mhz. tdd application figure 12 illustrates a typical tdd application circuit. the max19706 interfaces directly with the radio front- ends to provide a complete ?f-to-bits?solution for tdd applications. the max19706 provides several sys- tem benefits to digital baseband developers. fast time-to-market high-performance, low-power analog functions low risk, proven analog front-end solution no mixed-signal test times no nre charges no ip royalty charges enables digital baseband to scale with 65nm to 90nm cmos figure 9. balun transformer-coupled differential-to-single- ended output drive for tx dac max19706 idp idn v out qdp qdn v out figure 10. single-ended drive for rx adc max19706 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf qap qan com iap ian 0.1 f r iso 50 ? r iso 50 ? refp refn v in 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 31 figure 12. typical application circuit for tdd radio dac1 rx-i rx encode max 19706 802.11x zif transceiver agc tcxo 10-bit dac 10-bit adc 12-bit dac tx source half- duplex bus digital baseband asic t/r d9 d0 system control clk dist spi reg ref 1.024v buffer rx-q tx-i tx-q dac3 dac2 4:1 mux 10-bit, 333ksps v dd battery voltage monitor temperature measure 0v dd adc clk sclk din cs shdn dout refin refp refn com figure 11. rx adc dc-coupled differential drive max19706 iap com ian r iso 22 ? r iso 22 ? r11 600 ? r9 600 ? r3 600 ? r2 600 ? r1 600 ? r10 600 ? r8 600 ? r5 600 ? r4 600 ? r7 600 ? r6 600 ? c in 5pf c in 5pf
max19706 10-bit, 22msps, ultra-low-power analog front-end 32 ______________________________________________________________________________________ 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (0.5 lsb) at step 001 (0.25 lsb) 111 digital input code analog output value figure 13a. integral nonlinearity 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-0.25 lsb) differential linearity error (+0.25 lsb) 1 lsb 1 lsb digital input code analog output value figure 13b. differential nonlinearity grounding, bypassing, and board layout the max19706 requires high-speed board layout design techniques. refer to the max19707 ev kit data sheet for a board layout reference. place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. bypass v dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? capacitor. bypass ov dd to ognd with a 0.1? ceramic capacitor in parallel with a 2.2? capacitor. bypass refp, refn, and com each to gnd with a 0.33? ceramic capacitor. bypass refin to gnd with a 0.1? capacitor. multilayer boards with separated ground and power planes yield the highest level of signal integrity. use a split ground plane arranged to match the physical loca- tion of the analog ground (gnd) and the digital output- driver ground (ognd) on the device package. connect the max19706 exposed backside paddle to gnd plane. join the two ground planes at a single point so the noisy digital ground currents do not inter- fere with the analog ground plane. the ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. make this connection with a low-value, surface- mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system? ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensi- tive analog traces. make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. dynamic parameter definitions adc and dac static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the device are measured using the best-straight-line fit (dac figure 13a). differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes (adc) and a monotonic transfer function (adc and dac) (dac figure 13b). adc offset error ideally, the midscale transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. dac offset error offset error (figure 13a) is the difference between the ideal and actual offset point. the offset point is the out- put value when the digital input is midscale. this error affects all codes by the same amount and usually can be compensated by trimming.
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 33 adc gain error ideally, the adc full-scale transition occurs at 1.5 lsb below full scale. the gain error is the amount of devia- tion between the measured transition point and the ideal transition point with the offset error removed. adc dynamic parameter definitions aperture jitter figure 14 shows the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 14). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error) and results directly from the adc? resolution (n bits): snr(max) = 6.02db x n + 1.76db (in db) in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise and distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 ? 6 are the amplitudes of the 2nd- through 6th-order harmonics. third harmonic distortion (hd3) hd3 is defined as the ratio of the rms value of the third harmonic component to the fundamental input signal. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f 1 and f 2 , are present at the inputs. the intermodulation prod- ucts are (f 1 ? 2 ), (2 ? f 1 ), (2 ? f 2 ), (2 ? f 1 ? 2 ), (2 ? f 2 ? 1 ). the individual input tone levels are at -7dbfs. 3rd-order intermodulation (im3) im3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, f 1 and f 2 , are present at the inputs. the 3rd-order intermodulation products are (2 x f 1 ? 2 ), (2 ? f 2 ? 1 ). the individual input tone levels are at -7dbfs. thd (v +v +v +v +v ) v 2 2 3 2 4 2 5 2 6 2 1 = ? ? ? ? ? ? ? ? 20 x log hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 14. t/h aperture timing
max19706 10-bit, 22msps, ultra-low-power analog front-end 34 ______________________________________________________________________________________ power-supply rejection power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ?%. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in so that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. note that the t/h performance is usually the limiting factor for the small-signal input bandwidth. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as the full- power bandwidth frequency. dac dynamic parameter definitions total harmonic distortion thd is the ratio of the rms sum of the output harmonics up to the nyquist frequency divided by the fundamental: where v 1 is the fundamental amplitude and v 2 through v n are the amplitudes of the 2nd through nth harmonic up to the nyquist frequency. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component up to the nyquist frequency excluding dc. thd (v + v + ... + v ) v 2 2 3 2 n 2 1 = ? ? ? ? ? ? ? ? 20 x log selector guide part description sampling rate (msps) max19700 dual 10-bit rx adc, dual 10-bit tx dac, integrated td-scdma filters, three 12-bit auxiliary dacs 7.5 max19708 dual 10-bit rx adc, dual 10-bit tx dac, integrated td-scdma filters, three 12-bit auxiliary dacs, 10-bit auxiliary adc with 4:1 input mux 11 max19705/max19706/max19707 dual 10-bit rx adc, dual 10-bit tx dac, three 12-bit auxiliary dacs, 10-bit auxiliary adc with 4:1 input mux 7.5/22/45
max19706 10-bit, 22msps, ultra-low-power analog front-end ______________________________________________________________________________________ 35 clk serial interface and system control iap ian qap qan idp idn qdp qdn refp refn com dout refin din sclk cs system clock programmable offset/cm 1.024v reference buffer 10-bit adc 10-bit adc 10-bit dac half- duplex bus 10-bit dac 12-bit dac 12-bit dac 12-bit dac 4:1 mux gnd v dd 0v dd dac1 dac2 dac3 adc1 d0?9 shdn t/r max19706 10-bit adc adc2 ognd v dd = +2.7v to +3.3v ov dd = +1.8v to +3.3v functional diagram
max19706 10-bit, 22msps, ultra-low-power analog front-end 36 ______________________________________________________________________________________ 32, 44, 48l qfn .eps e l e l a1 a a2 e/ 2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k detail b e l l1 package outline 21-0144 2 1 e 32, 44, 48, 56l thin qfn, 7x7x0.8m m package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max19706 10-bit, 22msps, ultra-low-power analog front-end maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 37 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. quijano package outline 21-0144 2 2 e 32, 44, 48, 56l thin qfn, 7x7x0.8m m package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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